1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to a method and system for selecting a bus clock frequency of a data processing system. Still more particularly, the present invention relates to a method and system for dynamically setting the bus clock frequency of a data processing system in response to a number of loads.
2. Description of the Related Art
As microprocessor technology has continued to advance, the user's perception of the performance of a personal computer system is less determined by the clock frequency at which the central processing unit (CPU) operates and more determined by the data communication capabilities of the personal computer system. In a typical personal computer system, which may contain a CPU, one or more levels of memory, and a number of adaptor cards all coupled by one or more buses, the data communication capabilities of the personal computer system are determined in large measure by the throughput of the selected bus architecture. The throughput of the selected bus architecture is determined, in turn, by a number of factors, including the bandwidth of the bus, the bus clock frequency, and the overhead of the bus communication protocol.
Naturally, in order to enhance the performance of a computer system, it is desirable to increase the throughput of the selected bus architecture by increasing the bus clock frequency and/or bandwidth while decreasing the bus communication protocol overhead. One primary limitation on bus clock frequency is the number of loads connected to the bus. For example, the bus clock for a PCI (Peripheral Component Interconnect) local bus is permitted by the PCI specification to operate at any frequency between 0 and 66 Megahertz (MHz), but can only operate at maximum frequency if the PCI local bus has three or less loads. Otherwise, the PCI local bus is constrained to operate at a lower frequency. As a result, the current industry standard operating frequency for PCI local buses is 33 MHz, at which speed a PCI local bus can support up to ten loads.